This invention relates to programmable logic devices (“PLDs”) such as field-programmable gate arrays (“FPGAs”), and more particularly to circuitry for facilitating the performance of multiply-accumulate operations in PLDs.
PLDs typically include many identical or substantially identical blocks of programmable logic. A PLD may also include multiple instances of several other types of circuit blocks such as input/output (“I/O”) blocks, phase-locked loop and/or delay-locked loop (“PLL/DLL”) blocks, memory (e.g., RAM) blocks, digital signal processing (“DSP”) blocks, etc. These other types of blocks may be programmable with respect to some aspects of their operations. Typically, all of the functional blocks on a PLD can be interconnected in many different ways by interconnection resources of the PLD, which resources may also be programmable in various respects.
A typical capability of a DSP block on a PLD is the ability to perform a multiplication operation. The DSP blocks of some PLDs are not able to additionally accumulate (add) successive products produced by the DSP block, as is required to perform a multiply-accumulate (“MAC”) operation. If a MAC operation is required in such PLDs, the successive products produced by the DSP block must be accumulated in some of the more general-purpose programmable logic blocks of the PLD. This can have certain disadvantages such as relatively slow operation, use of significant numbers of programmable logic blocks that it might be desirable to have available for other purposes, use of significant amounts of interconnection resources (e.g., for routing DSP block products to the programmable logic blocks performing the accumulation), etc.